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CS4122 Triple Air-Core Gauge Driver with Serial Input Bus
The CS4122 converts digital data from a microprocessor to complementary DC outputs and drives air-core meter movements for vehicle instrument panels. It is optimized for one 360 gauge and two 112 gauges. The digital data controls the voltage applied to the quadrature coils of the meters with a 0.35 resolution for the major (360) gauge and 0.44 resolution for the minor (112) gauges. The accuracy is 0.75 for the major and 1.00 for the minors. The interface from the microcontroller is by a SPI compatible serial connection using up to a 2.0 MHz shift clock rate. The digital code is shifted into the appropriate DAC and multiplexer. These two blocks provide a tangential conversion function to change the digital data into the appropriate DC coil voltage. The major gauge driver can position a pointer anywhere within a 360 circle while the minor gauge drivers are limited to an arc of 112.2. The output buffers are capable of supplying up to 70 mA per coil and are protected against output short circuit conditions. A thermal protection circuit limits the junction temperature to approximately 160C. A fault output lead goes low when any of the outputs are shorted or the device is in a thermal shutdown state. This ASIC is designed on POWERSENSETM 3.0. Features Serial Input Bus 2.0 MHz Operating Frequency Independently Addressable Gauges Tangential Drive Algorithm 70 mA Drive Circuits 0.75 Major Accuracy Power-On-Reset Protection Features - Short Circuit - Overtemperature * Internally Fused Leads in SO-24L Package
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SO-24L DWF SUFFIX CASE 751E 1
24
MARKING DIAGRAM
24 CS4122 AWLYYWW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
* * * * * * * *
PIN CONNECTIONS
SCLK CS SIN- SIN+ GND GND GND GND VBB/2 C1+ C1- VCC 1 24 SO SI COS+ COS- GND GND GND GND C2- C2+ VBB FAULT
ORDERING INFORMATION
Device CS4122XDWF24 CS4122XDWFR24 Package SO-24L SO-24L Shipping 31 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
November, 2000 - Rev. 6
Publication Order Number: CS4122/D
CS4122
VCC VBB
POR SI SCLK SO Serial to Parallel Shift Register (12 bits) 8 Data 7 Decode/ Latch 2 Address Decode + Diag 8 FAULT 10 Data 7 Decode/ Latch 7 Bit DAC D7 D8 - D9
VTOP VVAR VBOT MUX
SIN+
SIN-
COS+
CS
VTOP 7 Bit DAC VVAR MUX
COS-
C1+ C1- 1/2 VBB VBB/2 MUX C2+
D7
VTOP Data 7 Decode/ Latch 7 Bit DAC D7 VVAR
C2- Fault Latch POR Over Temperature GND OE OC
Output Amplifiers
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating Supply Voltage Digital Inputs Steady State Output Current Forced Injection Current (Inputs and Supply) Operating Junction Temperature (TJ) Storage Temperature Range (TSTG) JA (Thermal Resistance Junction to Ambient) JC (Thermal Resistance Junction to Case) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) VBB VCC Value -1.0 to 16.5 -1.0 to 6.0 -1.0 to 6.0 100 10 150 -65 to 150 55 9 230 peak Unit V V V mA mA C C C/W C/W C
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ELECTRICAL CHARACTERISTICS (-40C TA 105C, 7.5 V VBB 14 V, 4.5 V VCC 5.5 V;
unless otherwise specified.) Characteristic Supply Voltages and Currents Analog Supply Current VBB = 14 V, no coil loads, RCOS, RSIN = RL(MIN) Major @ 45 (code = 08016), Both Minors @ 0 (codes = 0016) Major @ 0 (code = 00016), Both Minors @ 56 (codes = 8016) VCC = 5.5 V SCLK = 2.0 MHz SCLK = 0 MHz, VBB = 0 V - - - - - - 25 340 100 mA mA mA Test Conditions Min Typ Max Unit
Logic Supply Current
- -
- -
2.0 1.5
mA mA
Digital Inputs and Outputs Output High Voltage Output Low Voltage Output High Current Input High Voltage Input Low Voltage Input High Current Input Low Current Analog Outputs Output Function Accuracy Output Shutdown Current, Source and Sink Major Coil Drive Output Voltage Minor Coil Drive Output Voltage VBB/2 Minimum Load Resistance Major Accuracy Minor Accuracy VBB = Max VBB = Min - - IDR(VBB/2) = 50 mA TA = 105C TA = 25C TA = -40C - - - 0.75 V to VCC - 1.2 V; CL = 90 pF VCC - 1.2 V to 0.75 V; CL = 90 pF CL = 90 pF - - - - - - 70 43 - - (0.5 x VBB) - 0.1 229 171 150 - 175 175 - - - 75 75 0 75 - - - - 0.748 x VBB 0.744 x VBB - - - - - - - - - - - - - - 0.75 1.00 - - - - (0.5 x VBB) + 0.1 - - - 2.0 - - 100 100 150 - - - - deg deg mA mA V V V MHz ns ns ns ns ns ns ns ns ns SO = IOUT(HIGH) = 0.8 mA SO = IOUT(LOW) = 1.5 mA FAULT, IOUT(LOW) = 2.8 mA FAULT, VCC = 5.0 V, VOUT(HIGH) = VCC CS, SCLK, SI CS, SCLK, SI CS, SCLK, SI, VIN = 0.7 x VCC CS, SCLK, SI, VIN = 0.3 x VCC VCC - 0.8 - - - 0.7 x VCC - - - - - - - - - - - - 0.4 0.8 25 - 0.3 x VCC 1.0 1.0 V V V A V V A A
SCLK Frequency SCLK High Time SCLK Low Time SO Rise Time SO Fall Time SO Delay Time SI Setup Time SI Hold Time CS Setup Time CS Hold Time
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CS4122
PIN FUNCTION DESCRIPTION
PACKAGE PIN # SO-24L 1 PIN SYMBOL SCLK FUNCTION Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift register and the falling edge changes the data on SO. When High, allows data at SI to be shifted into the internal shift register with the rising edge of SCLK. The falling edge transfers the shift register contents into the DAC and multiplexer to update the output buffers. The falling edge also re-enables the output drivers if they have been disabled by a fault. Negative output for SINE coil. Positive output for SINE coil. Ground for VBB and VCC supplies. In the power SOIC package they aid in removing internally generated heat from the package and as such should be soldered to as large a PCB area as possible. Set to 1/2 VBB for biasing the two externally driven minor coils. Positive output for the #1 minor coil. Negative output for the #1 minor coil. 5.0 V logic supply. The internal registers and latches are reset by a POR generated by the rising edge of the voltage on this lead. Reflects the state of the output buffers. A logic low on this lead indicates that an output is shorted or the device is in thermal shutdown. Analog supply. Nominally 12 V. Positive output for the #2 minor coil. Negative output for the #2 minor coil. Negative output for COSINE coil. Positive output for COSINE coil. Serial data input. Data present at the rising edge of the clock signal is shifted into the internal shift register. Serial data output. Existing 12 bit data is shifted out when new data is shifted in. Allows cascading of multiple devices on common serial port.
2
CS
3 4 5, 6, 7, 8, 17, 18, 19, 20
SIN- SIN+ GND
9 10 11 12
VBB/2 C1+ C1- VCC
13
FAULT
14 15 16 21 22 23 24
VBB C2+ C2- COS- COS+ SI SO
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CS4122
APPLICATIONS INFORMATION
THEORY OF OPERATION Quadrant II q + 180 * Tan-1 (VSIN) * (VSIN*) ) (VCOS) * (VCOS*) )
The CS4122 is for interfacing between a microcontroller or microprocessor and air-core meters commonly used in automotive vehicles for speedometers, tachometers and auxiliary gauges. These meters are built using 2 coils placed at 90 orientation to each other. A magnetized disc floats in the middle of the coils and responds to the magnetic field generated by each coil. The disc has a shaft attached to it that protrudes out of the assembly. A pointer indicator is attached to this shaft and in conjunction with a separate printed scale displays the vehicle's speed, engine's speed or other information such as fuel quantity or battery voltage. The disc (and pointer) respond to the vector sum of the voltages applied to the coils. Ideally, this relationship follows a sine/cosine equation. Since this is a transcendental and non-linear function, devices of this type use an approximation for this relationship. The CS4122 uses a tangential algorithm as shown in Figure 2 for the major (360) gauge. Only one output varies in any 45 range. Note: The actual slopes are segmented but are shown here as straight lines for simplicity.
Degrees of Rotation
0 Max(128) 45 90 135 180 225 270 315 360
For q + 90.176to 134.824 : VSIN + 0.748 VBB 0.748 VBB VCOS + *Tan (q * 90) For q + 135.176to 179.824 : VSIN + Tan(180 * q) VCOS + *0.748 Quadrant III q + 180 ) Tan-1 (VSIN) * (VSIN*) ) (VCOS) * (VCOS*) ) VBB 0.748 VBB
For q + 180.176to 224.824 : VSIN + *Tan (q * 180) VCOS + *0.748 VSIN + *0.748 VBB 0.748 VBB
For q + 225.176to 269.824 : VBB 0.748 VBB VCOS + *Tan (270 * q) Quadrant IV q + 360 * Tan-1 (VSIN) * (VSIN*) ) (VCOS) * (VCOS*) )
SIN+ Output
Min(0) Max(128)
SIN- Output
For q + 270.176to 314.824 :
Min(0)
VSIN + *0.748
VBB 0.748 VBB
Max(128)
VCOS + Tan(q * 270) VSIN + *Tan (360 * q) VCOS + 0.748 VBB
COS+ Output
Min(0)
For q + 315.176 * 359.824 : 0.748 VBB
Max(128)
COS- Output
Min(0) 000 001 010 011 100 101 110 111 000
VCOS+ 360/0 0.748 VBB IV I 270 VSIN- 0.748 VBB III 0.748 VBB II 90 VSIN+
MUX bits (D9-D7)
Figure 2. Major Gauge Outputs Quadrant I (VSIN)) * (VSIN*) q + Tan-1 (VCOS)) * (VCOS*) For q + 0.176to 44.824 : VSIN + Tanq 0.748 VCOS + 0.748 VBB For q + 45.176to 89.824 : VSIN + 0.748 VBB VCOS + Tan(90 * q) 0.748 VBB http://onsemi.com
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VBB
0.748 VBB 180 VCOS-
Figure 3. Major Gauge Response
CS4122
The minor gauge coil outputs differ in that only one of the coils in each movement is driven by the IC. The other is driven directly by the analog supply voltage, specifically one-half of this voltage. The common output assures that this is true. By varying the voltage across the other coil to a greater voltage, the pointer can be deflected more than 45 to each side of the externally driven coil. This relationship is shown in Figure 4. Note: There are actually 8 segments, but only 3 are shown here for simplicity.
Degrees of Rotation
0 Max(128) 14 28 42 56 70 84 98 112
MSB Major Gauge (360) Gauge D9 - D7 select Address = "00" which octant
LSB Divides a 45 octant into 128 equal parts to achieve a 0.35 resolution Code 0 - 12710
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Gauge #1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gauge Address = "01" Set to "00" Deflection angle 0 - 112.2, to achieve a 0.44 resolution Code 0 - 25510
Minor Gauge #2
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gauge Address = "10" Set to "00" Deflection angle 0 - 112.2, to achieve a 0.44 resolution Code 0 - 25510
C+ Output
Min(0)
Max(128)
C- Output
Min(0) 00 1F 3F 5F 7F 9F BF DF FF
All D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gauges All Outputs Disabled; D9 - D0 = "Don't Care" Disabled Gauge Address = "11"
Code16
Figure 6. Definition of Serial Word Table 1. Nominal Output for Major Gauge (VBB = 14 V)
Figure 4. Minor Gauge Outputs Quadrant I, II (VC)) * (VC*) q + 56.1 * Tan-1 VBB * V(VBB 2) VCOIL + V(VBB 2) Tan (56.1 * q)
Input Code (Decimal) 0 128 256 384
Ideal Degrees 0 45 90 135 180 225 270 315 359.65
Nominal Degrees 0.176 45.176 90.176 135.176 180.176 225.176 270.176 315.176 359.826
VSIN (V) 0.032 10.472 10.472 10.412 -0.032 -10.472 -10.472 -10.476 -0.032
VCOS (V) 10.472 10.412 -0.032 -10.472 -10.472 -10.412 0.032 10.412 10.472
56.1 VBB/2
512 640 768
0 (-56.1) I VC+
II 0.744 VBB
112.2
896 1023
0.744 VBB
VC-
Table 2. Nominal Output for Minor Gauges (VBB = 14 V)
Input Code (Decimal) 0 127 128 255 Scale Degrees 0 55.88 56.32 112.2 Degrees from Center -56.1 -0.22 0.22 56.1 VCOIL 10.417 0.027 -0.027 -10.417
Figure 5. Minor Gauge Outputs
To drive a gauge's pointer to a particular angle, the microcontroller sends a 12 bit digital word to the CS4122. These 12 bits are divided as shown in Figure 6. However, from a software programmer's viewpoint, a 360 circle is divided into 1024 equal parts of .35 each and a 112.2 arc is divided into 256 parts of .44 each. Table 1 shows the data associated with the 45 divisions of the 360 driver. Table 2 shows the data for the center and end points of the 112.2 drivers. Setting the address to "11" disables all outputs.
The 12 bits are shifted into the device's shift register MSB first using a SPI compatible scheme. This method is shown in Figures 6 and 7. The first 2 bits select the output driver for which the data is intended. The CS must be high and remain high for SCLK to be enabled. Data on SI is shifted in on the
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CS4122
rising edge of the synchronous clock signal. Data in the shift register is shifted to SO on the falling edge of SCLK. This arrangement allows the cascading of devices. SO is always enabled. Data shifts through without affecting the outputs until CS is brought low. At this time, the internal DAC is updated and the outputs change accordingly.
CS
CSSetup CSHold
SCLK
SI(Setup) SI(Hold)
SI SO
SO(tpd) SO(Rise, Fall) 10% - 90%
Figure 7. Serial Data Timing Diagram
The DAC for the major gauge driver outputs 128 discrete levels selected by bits D6 - D0. These bits are XOR'd with D7 to invert them when choosing the 2nd half of each quadrant (each odd octant). This reduces the number of
resistors and switches required. The MUX chooses which signals to send to the output amplifiers based upon D9 - D7. There are three choices for each amplifier: high, low or the DAC output. The DAC's for the minor gauge drivers similarly output 128 discrete levels selected by bits D6 - D0. These bits are also XOR'd with D7 to invert them when choosing the 2nd half of the output range. The MUX chooses which signals to send to the output amplifiers based upon D7. There are two choices for each amplifier; high or the DAC output. Bits D8 and D9 are not used, but should be set to "00" to ensure that the minor gauge outputs are enabled. The output buffers are unity gain amplifiers. Each of the 8 outputs is designed to swing close to the supply rails to maximize the voltage across the coils to produce maximum torque. Additionally, this lowers the power dissipation. The current for each output is also monitored. If any of the major gauge outputs exceed the maximum value, all of the major outputs are disabled. If any of the minor gauge outputs exceed the maximum value, all of the minor outputs are disabled. The falling edge of the CS re-enables the outputs with the fault condition but they remain on only if the overcurrent situation has been eliminated.
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CS4122
VREG CS8156 ENABLE 5.0 V 12 V
VBAT
360 Gauge SIN- SIN+ FAULT CS Microcontroller From Vehicle Sensors SI SCLK C1- C1+ CS4122 COS+ COS- VBB VCC SO Next Driver C2+ C2- VBB/2
112 Gauges
Figure 8. Application Diagram
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CS4122
PACKAGE DIMENSIONS
SO-24L DWF SUFFIX CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-24L 9 55 Unit C/W C/W
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CS4122
Notes
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CS4122
Notes
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CS4122
POWERSENSE is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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CS4122/D

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